Error correction decoding device and reproduction device

ABSTRACT

A decoding device which performs error correction decoding of encoded data formed from a combination of an outer code for first error correction and an inner code for second error correction is disclosed. The decoding device has: a demodulator for creating a data series of likelihood information values; a second error correction decoder for creating a hard decision value series by executing repetitive decoding for the second error correction based on the likelihood information values; and a first error correction decoder for detecting a lost bit in the hard decision value series and creating an erasure flag indicating the position of the detected lost bit. The second error correction decoder, according to the erasure flag, executes the repetitive decoding based on a likelihood information value not corresponding to the position of the lost bit among the data series of the likelihood information values and a predetermined value that invalidates the likelihood information value corresponding to the position of the lost bit.

TECHNICAL FIELD

The present invention relates to decoding technology of error correctioncodes, and in particular relates to decoding technology of concatenatedcodes and iterated codes formed from the combination of an outer codeand an inner code.

BACKGROUND ART

Error correction technology is essential technology for realizing highlyreliable communication systems and information recording systems.Concatenated codes and iterated codes are codes that are formed from acombination of two types of codes (outer code and inner code). Forinstance, an RS code (Reed-Solomon code) or a BCH code(Bose-Chaudhuri-Hocquenghem code) is broadly used as the outer code, anda convolutional code, a turbo code or an LDPC code (Low Density ParityCheck code) is broadly used as the inner code. In particular, the turbocode and the LDPC code are attracting attention as an error correctioncode for realizing performance that approaches the Shannon limit. TheLDPC code and its decoding method are disclosed, for example, in PatentDocument 1 (Japanese Patent Kokai 2006-279396).

Additionally, research on decoding algorithms having high errordetection performance regarding the foregoing error correction codes isbeing conducted. Signals read from a recording medium such as an opticaldisk or an HD (hard disk) is not only susceptible to random errors, theyare also susceptible to burst errors resulting from the damage of therecording medium or mechanical operation of the reproduction device.Decoding algorithms for detecting burst errors with high precision aredisclosed, for example, in Patent Document 2 (Japanese Patent Kokai No.2004-127408) and Patent Document 3 (Kokai No. 2005-166089).Nevertheless, since much time is required for the decoding processing ifthe error detection rate of the decoding algorithm becomes higher, thereis a problem in that this may cause deterioration in the throughput.

Patent Document 1: Japanese Patent Kokai No. 2006-279396

Patent Document 2: Japanese Patent Kokai No. 2004-127408

Patent Document 3: Japanese Patent Kokai No. 2005-166089

DISCLOSURE OF THE INVENTION

A first objective of the present invention in light of the above is toprovide an error correction decoding device and a reproduction devicecapable of realizing extremely high error correction performance. Thesecond object of the present invention is to provide an error correctiondecoding device and a reproduction device capable of improving thethroughput while realizing high error correction performance.

The error correction decoding device according to a first aspect is adecoding device for performing error correction decoding of encoded dataformed from a combination of an outer code for first error correctionand an inner code for second error correction. This decoding device has:a demodulator for demodulating the encoded data and creating a dataseries of likelihood information values; a memory circuit fortemporarily storing the data series of likelihood information values; asecond error correction decoder for creating a hard decision valueseries by executing repetitive decoding for the second error correctionbased on the data series of likelihood information values read from thememory circuit; and a first error correction decoder for detecting alost bit in the hard decision value series by executing algebraicdecoding for the first error correction to the hard decision valueseries and creating an erasure flag indicating a position of thedetected lost bit. With this decoding device, the second errorcorrection decoder, according to the erasure flag, re-reads the dataseries of likelihood information values from the memory circuit, andexecutes the repetitive decoding based on a likelihood information valuenot corresponding to the position of the lost bit among the re-read dataseries and a predetermined value that invalidates a likelihoodinformation value corresponding to the position of the lost bit amongthe re-read data series.

The error correction decoding device according to a second aspect of thepresent invention is a decoding device for performing error correctiondecoding of encoded data formed from a combination of an outer code forfirst error correction and an inner code for second error correction.This decoding device has: a demodulator for demodulating the encodeddata and creating a data series of likelihood information values; a lostposition detection part for detecting a lost bit in the data series oflikelihood information values and creating a first erasure flagindicating a position of the detected lost bit; a memory circuit fortemporarily storing the data series of likelihood information values; asecond error correction decoder for creating a hard decision valueseries by executing repetitive decoding for the second error correctionbased on the data series likelihood information values read from thememory circuit when the lost bit is not detected, and a first errorcorrection decoder for executing algebraic decoding for the first errorcorrection to the hard decision value series. With this decoding device,when the lost bit is detected, the second error correction decoderexecutes the repetitive decoding based on a likelihood information valuenot corresponding to the position of the lost bit among the data seriesof likelihood information values read from the memory circuit and apredetermined value that invalidates a likelihood information valuecorresponding to the position of the lost bit among the read data seriesof likelihood information values.

The reproduction device according to a third aspect of the presentinvention is a reproduction device for reading encoded data formed froma combination of an outer code for first error correction and an innercode for second error correction from a recording medium, and performingerror correction decoding of the read encoded data. This reproductiondevice has: a driver part for driving the recording medium and readingthe encoded data from the recording medium; a demodulator fordemodulating the read encoded data and creating a data series oflikelihood information values, a memory circuit for temporarily storingthe data series of likelihood information values; a second errorcorrection decoder for creating a hard decision value series byexecuting repetitive decoding for the second error correction based onthe data series likelihood information values read from the memorycircuit; and a first error correction decoder for detecting a lost bitin the hard decision value series by executing algebraic decoding forthe first error correction to the hard decision value series andcreating an erasure flag indicating a position of the detected lost bit.With this reproduction device, the second error correction decoder,according to the erasure flag, re-reads the data series of likelihoodinformation values from the memory circuit, and executes the repetitivedecoding based on a likelihood information value not corresponding tothe position of the lost bit among the re-read data series and apredetermined value that invalidates a likelihood information valuecorresponding to the position of the lost bit among the re-read dataseries.

The reproduction device according to the fourth aspect of the presentinvention is a reproduction device for reading encoded data formed froma combination of an outer code for first error correction and an innercode for second error correction from a recording medium, and performingerror correction decoding of the read encoded data. This reproductiondevice has: a driver part for driving the recording medium and readingthe encoded data from the recording medium; a demodulator fordemodulating the encoded data and creating a data series of likelihoodinformation values, a lost position detection part for detecting a lostbit in the data series of likelihood information values and creating afirst erasure flag indicating a position of the detected lost bit; amemory circuit for temporarily storing the data series of likelihoodinformation values; a second error correction decoder for creating ahard decision value series by executing repetitive decoding for thesecond error correction based on the data series likelihood informationvalues read from the memory circuit when the lost bit is not detected,and a first error correction decoder for executing algebraic decodingfor the first error correction to the hard decision value series. Withthis reproduction device, when the lost bit is detected, the seconderror correction decoder executes the repetitive decoding based on alikelihood information value not corresponding to the position of thelost bit among the data series of likelihood information values readfrom the memory circuit and a predetermined value that invalidates alikelihood information value corresponding to the position of the lostbit among the read data series of likelihood information values.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram showing a schematic configurationof a recording/reproduction device as the first embodiment of thepresent invention.

FIG. 2A and FIG. 2B are diagrams showing an example of an errorcorrection code format of encoded data.

FIG. 3 is a diagram showing another example of an error correction codeformat of encoded data.

FIG. 4 is a block diagram showing a configuration of an error correctiondecoding part according to the first embodiment.

FIG. 5 is a block diagram showing a configuration of an error correctiondecoding part according to a modified example of the first embodiment.

FIG. 6 is a flowchart schematically showing an operation routine of theerror correction decoding part according to the first embodiment.

FIG. 7 is a flowchart showing a processing routine of a second errorcorrection code according to the first embodiment.

FIG. 8 is a diagram explaining the Sum-Product decoding method.

FIG. 9A to FIG. 9C are diagrams explaining the message passing algorithmof the Sum-Product decoding method.

FIG. 10 is a flowchart showing a processing routine of a second errorcorrection code according to a modified example of the first embodiment.

FIG. 11 is a functional block diagram showing a schematic configurationof a recording/reproduction device as the second embodiment of thepresent invention.

FIG. 12 is a block diagram showing a configuration of an errorcorrection decoding part according to the second embodiment.

FIG. 13 is a flowchart schematically showing an operation routine of anerror correction decoding part according to the second embodiment.

FIG. 14 is a flowchart showing a processing routine of a second errorcorrection code according to the second embodiment.

FIG. 15 is a functional block diagram showing a schematic configurationof a recording/reproduction device as the third embodiment of thepresent invention.

FIG. 16 is a block diagram showing a configuration of an errorcorrection decoding part according to the third embodiment.

FIG. 17 is a circuit diagram showing an example of a configuration of anextraction control part according to the third embodiment.

FIG. 18 is a circuit diagram showing another example of a configurationof an extraction control part according to the third embodiment.

FIG. 19 is a circuit diagram showing yet another example of aconfiguration of an extraction control part according to the thirdembodiment.

FIG. 20 is a flowchart schematically showing an operation routine of anerror correction decoding part according to the third embodiment.

FIG. 21 is a functional block diagram showing a schematic configurationof a recording/reproduction device as the fourth embodiment of thepresent invention.

FIG. 22 is a block diagram showing a configuration of an errorcorrection decoding part according to the fourth embodiment.

FIG. 23 is a flowchart schematically showing an operation routine of anerror correction decoding part according to the fourth embodiment.

FIG. 24 is a functional block diagram showing a schematic configurationof a recording/reproduction device as the fifth embodiment of thepresent invention.

FIG. 25 is a block diagram showing a configuration of an errorcorrection decoding part according to the fifth embodiment.

EXPLANATION OF REFERENCE NUMERALS

-   -   1A, 1B, 1C, 1D, 1E recording/reproduction device    -   2 recording medium    -   3 driver part    -   11 first error correction coder    -   12 second error correction coder    -   21, 21P SISO demodulator (soft input soft output demodulator)    -   22A, 22B, 22C, 22D, 22E error correction decoding part    -   23, 43 SP converter (serial-parallel converter)    -   24 memory circuit    -   25 selection circuit    -   26 second error correction decoder    -   27 first error correction decoder    -   40 lost position detection part    -   41 extraction control part    -   42 gate circuit    -   44 error correction decoder    -   44 s decoding status determination part    -   70 selection circuit

BEST MODE FOR CARRYING OUT THE INVENTION

The various embodiments of the present invention are now explained.

First Embodiment

FIG. 1 is a functional block diagram showing a schematic configurationof a recording/reproduction device 1A as the first embodiment of thepresent invention. The recording/reproduction device 1A has a functionof recording input data (user data) Din in a recording medium 2, and afunction of reproducing the recorded data Dout from the recording medium2. The recording medium 2 may be, for example, optical discs such as aCD (Compact Disc), a DVD (Digital Versatile Disc), a BD (Blu-ray Disc)or an AOD (Advanced Optical Disc), or a holographic memory, aferroelectric probe memory or an HD (hard disk), and there is noparticular limitation. Incidentally, the error correction decodingtechnology explained below can also be applied to various fields, inaddition to the field of recording/reproduction devices, which requireerror correction decoding.

The recording/reproduction device 1A includes an error correction codingpart 10, a modulator 13, and a data adding part 14. The error correctioncoding part 10 includes a first error correction coder 11 and a seconderror correction coder 12. The error correction coding part 10 issupplied with input data Din to which a CRC code (Cyclic RedundancyCheck code) was added thereto. The first error correction coder 11creates an outer code as an algebraic error correction code such as aBCH code or an RS code (Reed-Solomon code), and adds this outer code tothe input data Din. The second error correction coder 12 creates aseries of code words formed from an LDPC code as an inner code based onthe output series of the first error correction coder 11. Here, it isalso possible to interpose an interleaver for interleaving the output ofthe first error correction coder 11 between the first error correctioncoder 11 and the second error correction coder 12, and interpose ade-interleaver for performing de-interleave of returning the order ofthe signals that were interleaved by the interleaver to the originalorder between the second error correction decoder 26 and the first errorcorrection decoder 27. Otherwise, it is also possible to interpose aninterleaver between the second error correction coder 12 and themodulator 13, and interpose a de-interleaver for performingde-interleave of returning the order of the signals that wereinterleaved by the interleaver to the original order between thedemodulator 21 and the memory circuit 24. Incidentally, interleaving isalso able to convert burst errors (continuously occurring errors) intorandom errors during the decoding process.

The modulator 13 modulates a code word series that is supplied from thesecond error correction coder 12 with a recording/modulation system thatis compliant with the specifications of the recording medium 2. Forinstance, if the recording medium 2 is an optical disk, the modulator 13is able to execute the publicly known RLL (Run-Length Limited)modulation, and if the recording medium 2 is a hologram memory, themodulator 13 is able to execute two-dimensional modulation such as thepublicly known 2-4 modulation. The data adding part 14 creates arecording signal by adding a synchronization detection pattern orinserting a position correction marker to the modulated signal suppliedfrom the modulator 13, and transfers the recording signal to the driverpart 3. The driver part 3 writes the transferred recording signal intothe recording medium 2.

FIG. 2A, FIG. 2B and FIG. 3 are respective diagrams schematicallyshowing an example of an error correction code format that may becreated with the error correction coding part 10. With the errorcorrection code format shown in FIG. 2A, the encoded data is formed froma data block configured from user data of b1 row×a3 column, an outercode block configured from an outer code (RS code) series of b1row×(a2−a3) column, and an inner code block configured from an innercode (LDPC code) series of b1 row×(a1−a2) column. The data block, theouter code block and the inner code block are arranged serially, and thedata block is arranged in an area of No. 0 column to No. (a3−1) column,the outer code block is arranged in an area of No. a3 column to No.(a2−1) column, and the inner code block is arranged in an area of No. a2column to No. (a1−1) column, respectively.

With the error correction code format shown in FIG. 2B, the encoded datais formed from a data block configured from user data of d2 row×c2column, an outer code block configured from an outer code (RS code)series of d2 row×(c1−c2) column, and an inner code block configured froman inner code (LDPC code) series of (d2−d1) row×c1 column. The datablock and the outer code block are arranged serially, and the inner codeblock is arranged parallel to the data block and the outer code block.The data block is arranged in an area of No. 0 row to No. (d2−1) row andNo. 0 column to No. (c2−1) column, the outer code block is arranged inan area of No. 0 row to No. (d2−1) row and No. c2 column to No. (c1−1)column, and the inner code block is arranged in an area of No. d2 row toNo. (d1−1) row and No. 0 column to No. (c1−1) column, respectively.

The error correction code format shown in FIG. 3 is a format in whichthe code block of f1 row×e1 column is sequenced three dimensionallyacross g1 code blocks. Each of the code blocks of No. 0 to No. (g2−1) isformed from a data block configured from user data of f2 row×e2 column,a first outer code block configured from an outer code (RS code) seriesof f2 row×(e1−e2) column, and a second outer code block configured froman outer code (RS code) series of (f1−f2) row×e1 column. The first outercode block and the second outer code block configure an iterated code.The data block is arranged in an area of No. 0 row to No. (f2−1) row andNo. 0 column to No. (e2−1) column, the first outer code block isarranged in an area of No. 0 row to No. (f2−1) row and No. e2 column toNo. (e1−1) column, and the second outer code block is arranged in anarea of No. f2 row to No. (f1−1) row and No. 0 column to No. (e1−1)column, respectively. Each of the remaining code blocks of No. g2 to No.(g1−1) is configured only from an inner code (LDPC code) series.

As shown in FIG. 1, the recording/reproduction device 1A includes, asfunctional blocks for reproducing the recorded data Dout from therecording medium 2, a driver part 3, an added data detection part 20, anSISO demodulator (soft input soft output demodulator) 21, and an errorcorrection decoding part 22A. The error correction decoding part 22Aincludes a memory circuit 24, a selection circuit 25, a second errorcorrection decoder 26, and a first error correction decoder 27. Asdescribed above, if an interleaver is provided between the first errorcorrection coder 11 and the second error correction coder 12, ade-interleaver for returning the sequence of the interleaved demodulatedsignal to the original sequence is provided between the second errorcorrection decoder 26 and the first error correction decoder 27.

The added data detection part 20 creates a reproduction sample valueseries by AD-converting the reproduction signal supplied from the driverpart 3. Moreover, the added data detection part 20 detects the foregoingsynchronization detection pattern or the position correction marker fromthe reproduction sample value series, and uses the synchronizationdetection pattern or the position correction marker to performpre-processing such as synchronization processing and geometricalcorrection to the reproduction sample value series. The added datadetection part 20 extracts the modulation sample value series from thepre-processed reproduction sample value series, and supplies theextracted modulation sample value series to the SISO demodulator 21.

The SISO demodulator 21 creates likelihood information Ld formed from alog likelihood ratio series as prior information representing thelikelihood regarding the respective modulation sample values, andprovides the likelihood information Ld to the error correction decodingpart 22A. The function of the SISO demodulator 21 is realized, forexample, by using the publicly known BCJR (Bahl-Cocke-Jelinek-Raviv)algorithm. Details regarding the BCJR algorithm are described, forinstance, in the Non-Patent Document of “L. R. Bahl, J. Cocke, F.Jelinek and J. Raviv, “Opti-mal decoding of linear codes for minimizingsymbol error rate,” IEEE Trans. IT, Vol. 20, 1974.”

In the error correction decoding part 22A, the memory circuit 24temporarily stores the likelihood information Ld created with the SISOdemodulator 21. The likelihood information Ld that was output from thememory circuit 24 is supplied to the second error correction decoder 26via the selection circuit 25. The second error correction decoder 26estimates the code word series based on the likelihood information Ldaccording to the decoding algorithm of the LDPC code, and supplies theseries of the hard decision values (binary series) to the first errorcorrection decoder 27. Although this embodiment uses the publicly knownSum-Product decoding method as the preferable decoding algorithm, thepresent invention is not limited thereto. The Sum-Product decodingmethod performs so-called repetitive decoding (repeated decoding) asdescribed later.

Generally speaking, turbo coding is executed by two coders that areconnected in parallel. Turbo decoding is executed by exchanginglikelihood information (outer log likelihood) between two soft inputsoft output decoders corresponding respectively to each of the foregoingcoders. Thus, turbo decoding also entails repetitive decoding. In thisembodiment, although the second error correction coder 12 adopts theLDPC coding system and the second error correction decoder 26 creates adeduced word series according to the Sum-Product decoding method, thepresent invention is not limited thereto. So as long as it is possibleto create a deduced word series by executing repetitive decoding, thesecond error correction decoder 26 may be any decoder that performsturbo decoding and other repetitive decoding (repeated decoding).

The first error correction decoder 27 has a function of executingalgebraic error correction decoding to the hard decision value seriessupplied from the second error correction decoder 26, and detecting alost bit (erasure) in symbol parts configured from predetermined bits.If a lost bit is detected, the first error correction decoder 27 createsan erasure flag Er indicating the position of the lost bit and suppliesthis to the selection circuit 25 and the second error correction decoder26. In the foregoing case, the second error correction decoder 26re-reads the data series of the log likelihood ratio from the memorycircuit 24 according to the erasure flag Er. Simultaneously, theselection circuit 25 supplies the log likelihood ratio that does notcorrespond to the position of the lost bit in the data series read fromthe memory circuit 24 to the second error correction decoder 26 as is inaccordance with the erasure flag Er, and supplies a predetermined valuethat invalidates the log likelihood ratio to the second error correctiondecoder 26 in substitute for the log likelihood ratio that correspondsto the position of the lost bit.

FIG. 4 is a diagram showing an example of the configuration of the errorcorrection decoding part 22A. As shown in FIG. 4, N log likelihoodratios λ₁, . . . , λ_(N) are supplied for each code word in parallelfrom the SISO demodulator 21 to the memory circuit 24. Each loglikelihood ratio λ_(k), (k is an arbitrary integer from 1 to N) has asoft output value. The selection circuit 25 has N selectors 28 ₁, . . ., 28 _(N), and a corresponding log likelihood ratio λ₁, . . . , λ_(N) isinput from the memory circuit 24 to one terminal D1 of the selectors 28₁, . . . , 28 _(N), and a predetermined value λ0 is input to the otherterminal D2. Moreover, a corresponding erasure flag Er₁, . . . , Er_(N)is supplied from the first error correction decoder 27 to the controlledterminal of the selectors 28 ₁, . . . , 28 _(N). Each selector 28 _(k)(k is an arbitrary integer from 1 to N) selects either the loglikelihood ratio λ_(k) or the predetermined value λ₀ that invalidatesthe log likelihood ratio λ_(k) according to the value (“0” or “1”) ofthe erasure flag Erk, and supplies the selected value to the seconderror correction decoder 26.

The second error correction decoder 26 creates deduced words e₁, . . . ,e_(N) by performing Sum-Product decoding to the likelihood informationsupplied from the selection circuit 25, and supplies the deduced wordse₁, . . . , e_(N) to the first error correction decoder 27. Theprocessing routine of the Sum-Product decoding method will be describedlater.

In the configuration shown in FIG. 4, although the selection circuit 25is configured from N selectors 28 ₁, . . . , 28 _(N), if thepredetermined value λ0 is “0” and the resolution of each log likelihoodratio λ_(k) (k is an arbitrary integer from 1 to N) is M bits, asillustrated in FIG. 5, the selection circuit 25 may also be configuredfrom N logic circuits 29 ₁ to 29 _(N). As shown in FIG. 5, each loglikelihood ratio λ_(k) is configured from M bits λ_(k)[0] to λ_(k)[M−1].Each logic circuit 29 _(k) (k is an arbitrary integer from 1 to N) has MAND gates 300 to 30M−1 corresponding respectively to the bits λ_(k)[0]to λ_(k)[M−1]. Each AND gate 30 i belonging to the logic circuit 29 _(k)alternates the bit of the erasure flag Erk, performs logical ANDoperation to the alternating bit and the bit λ_(k)[i] of the loglikelihood ratio λ_(k), and provides the operation result to the seconderror correction decoder 26.

The processing routine of the foregoing error correction decoding part22A is now explained with reference to FIG. 6 and FIG. 7. FIG. 6 is aflowchart schematically explaining a part of the processing routine tobe performed by the error correction decoding part 22A.

When the second error correction decoder 26 receives data of the loglikelihood ratios λ₁ to λ_(N) from the selection circuit 25, itcalculates the deduced words e₁ to e_(N) by executing LDPC decodingbased on the log likelihood ratios λ₁ to λ_(N) (step S10). Here, thefirst error correction decoder 27 sets the value of the erasure flagsEr₁ to Er_(N) to be supplied to the selection circuit 25 to the initialvalue (=“0”). Thus, the selection circuit 25 supplies the data of alllog likelihood ratios λ₁ to λ₁ received from the memory circuit 24 tothe second error correction decoder 26 as is.

Subsequently, the first error correction decoder 27 performs algebraicerror correction decoding such as RS decoding to the deduced words e₁ toe_(N), and outputs the decoding result as the user data Dout (step S11).If the first error correction decoder 27 detects a lost bit in theseries of the deduced words e₁ to e_(N) (step S12), the first errorcorrection decoder 27 creates erasure flags Er₁ to Er_(N) indicating theposition of the lost bit, and thereafter supplies the created erasureflags Er₁ to Er_(N) to the selection circuit 25 (step S13).

After the creation of the erasure flags Er₁ to Er_(N) (step S13), thesecond error correction decoder 26 re-reads the log likelihood ratios λ₁to λ_(N) corresponding to the lost bit from the memory circuit 24 incode word parts (step S14). The re-read log likelihood ratios λ₁ toλ_(N) are supplied to the selection circuit 25. The selection circuit 25supplies the log likelihood ratio λ_(k) to the second error correctiondecoder 26 if the value of the erasure flag Erk is “0,” and supplies apredetermined value λ0 to the second error correction decoder 26 insubstitute for the log likelihood ratio λ_(k) if the value of theerasure flag Erk is “1.” Then, the second error correction decoder 26returns to the processing of step S10 and executes LDPC decoding. Theroutine of steps S10 to S14 is thereafter repeatedly executed until itis determined that a lost bit is not detected at step S12.

If the first error correction decoder 27 does not detect a lost bit inthe series of the deduced words e₁ to e_(N) at step S12, and acontroller (not shown) does not issue a command to end the decodingprocessing (step S15), the second error correction decoder 26 returns tostep S10 and continues the LDPC decoding. Meanwhile, if a command forending the decoding processing is issued (step S15), the foregoingdecoding processing is ended.

The processing routine of the Sum-Product decoding (LDPC decoding) to beperformed by the second error correction decoder 26 is now explainedwith reference to FIG. 7. FIG. 7 is a flowchart showing the processingroutine of the Sum-Product decoding.

The LDPC code is a simulated random code that is created by using anon-dense parity check matrix H of M rows and N columns. Sum-Productdecoding, which is one decoding method of the LDPC code, is a messagepassing algorithm that is expressed by using a Tanner graph (bigraph)configured from a parity check matrix H. FIG. 8 illustrates a Tannergraph configured from a parity check matrix H of 3 rows and 7 columns.As shown in FIG. 8, the Tanner graph is configured from variable nodes(message nodes) v₁ to v₇ respectively corresponding to the columns ofthe check matrix H, and check node m₁ to m₃ respectively correspondingto the rows of the check matrix H. With a Tanner graph, only when theelement of i row and j column of the check matrix H is a non-zeroelement (=1), the distance between the jth variable node v_(j) and thejth check node m_(j) is connected with a line referred to as an “edge.”The number of edges to be connected to the ith check node m_(i) isequivalent to the humming weight (row weight) of i row of the checkmatrix H, and the number of edges to be connected to the jth variablenode v_(j) is equivalent to the humming weight (column weight) of j rowof the check matrix H. It could be said that the Sum-Product decodingmethod is a method of calculating the approximate posterior probabilityin symbol units or bit units by exchanging messages in the foregoingTanner graph.

Upon referring to FIG. 7, the second error correction decoder 26performs initialization to the log likelihood ratios λ₁ to λ_(N) of therespective code words (step S20). Here, the variable i representing theiteration count is set to “1,” and all prior values (log prior valueratios) β_(m, n) corresponding to the non-zero element of m row and ncolumn of the check matrix H are set to “0.” Incidentally, the loglikelihood ratio λ_(k) is generally defined by the following Formula(1).

$\begin{matrix}{\lambda_{k}:={\ln {\frac{P\left( {{c_{k}x_{k}} = 0} \right)}{P\left( {{c_{k}x_{k}} = 1} \right)}.}}} & (1)\end{matrix}$

Here, x_(k) represents the kth element of the original code word x=(x₁,x₂, . . . , x_(N)) created by the second error correction coder 12 (FIG.1), and c_(k) represents the kth elements of the code word c=(c₁, c₂, .. . , c_(N)) read from the recording medium 2. P (B|A) is theconditional probability that event B will occur when event A occurs.

If the recording system including the recording medium 2 is an AWGN(Additive White Gaussian Noise) channel, it is known that the loglikelihood ratio λ_(k) can be calculated based on the following Formula(1a).

$\begin{matrix}{\lambda_{k} = {{\ln \frac{P\left( {{c_{k}x_{k}} = 0} \right)}{P\left( {{c_{k}x_{k}} = 1} \right)}} = {\frac{2}{\sigma^{2}}{c_{k}.}}}} & \left( {1\; a} \right)\end{matrix}$

Here, σ² is the dispersion of gaussian noise.

Nevertheless, in reality, since factors such as modulated strain andjitter also affect the log likelihood ratio λ_(k) in addition to thegaussian noise, it would be undesirable to use the log likelihood ratioλ_(k) that is simply subject to only the AWGN channel. The SISOdemodulator 21 shown in FIG. 1 is designed to create the likelihoodinformation Ld so as to optimize the error correction performance of theLDPC decoding.

Subsequently, whether the variable i is less than or equal to the presetmaximum iteration count imax is determined (step S21). If the variable iis less than or equal to the maximum iteration count imax, at steps S22to S25, the outer values αm, n are updated by executing row processing(check node processing) in the order of row number m=1, 2, . . . , M.Specifically, it is determined whether at step S22 the row number m isset to “1” and whether at step S23 the row number m is M rows or less ofthe check matrix H. If the row number m is M rows or less of the checkmatrix H, the row processing regarding the mth row is executed (stepS24), the row number m is incremented (step S25), and the processingreturns to the routine of step S23.

More specifically, the row processing may be executed by calculating theouter values (log outer value ratios) am, n corresponding to thenon-zero element of mth row and nth column of the check matrix H in theorder of row number m=1, 2, . . . , M according to the following Formula(2).

$\begin{matrix}{\alpha_{m,n} = {\prod\limits_{n^{\prime} \in {{A{(m)}}\backslash \; n}}\; {{{sign}\left( {\lambda_{n^{\prime}} + \beta_{m,n^{\prime}}} \right)} \cdot {{\varphi\left( {\sum\limits_{n^{\prime} \in {{A{(m)}}\backslash \; n}}{\varphi \left( {{\lambda_{n^{\prime}} + \beta_{m,n^{\prime}}}} \right)}} \right)}.}}}} & (2)\end{matrix}$

Here, A(m) is a set of the column number (column index) corresponding toa non-zero element existing in the mth row of the check matrix H. A(m)\nrepresents a set in which the element n has been removed from the setA(m). With the Tanner graph shown in FIG. 8, for example, A(1)={1, 2, 3,5}, and A(1)\1={2, 3, 5}.

The function sign (x) in foregoing Formula (1) is defined by thefollowing Formula (3).

$\begin{matrix}{{{sign}(x)}:=\left\{ \begin{matrix}{{+ 1},} & {{{for}\mspace{14mu} x} \geq 0} \\{{- 1},} & {{{for}\mspace{14mu} x} < 0}\end{matrix} \right.} & (3)\end{matrix}$

In addition, the function φ (x) in foregoing Formula (1) is referred toas the Gallager function, and is defined by the following Formula (4).

$\begin{matrix}{{\varphi (x)}:={{\ln \frac{{\exp (x)} + 1}{{\exp (x)} - 1}} = {{\ln \left( {\tanh \left( \frac{- x}{2} \right)} \right)}.}}} & (4)\end{matrix}$

To explain the calculation method of the outer value α_(1, 1) using theTanner graph, as shown in FIG. 9A, log likelihood ratios λ₁ to λ_(N) arerespectively provided to the variable nodes v₁ to v_(N). The check nodem₁ calculates the outer values α_(1, 1) based on a message supplied, viathe edge, from the variable nodes (message nodes) v₂, v₃, v5 designatedin the set A(1)\1. The variable node v₁ updates the old outer value withthe new outer value α_(1, 1) supplied from the check node m₁. Meanwhile,if the first error correction decoder 27 (FIG. 1) detects a lost bitonly at the 2nd position of the code word (step S13 of FIG. 6), thevalue of the erasure flag Er₂ is set to “1,” and the value of the othererasure flags Er₁, Er₃ to Er₇ is set to “0.” Here, as shown in FIG. 9B,a predetermined value λ₀ is provided to the variable node v₂, and thelog likelihood ratios λ₁, λ₃ to λ_(N) are respectively provided to theother variable nodes v₁, v₃ to v_(N).

Subsequently, at steps S26 to S29, the prior value βm, n is updated byexecuting column processing (message node processing) in the order ofcolumn number n=1, 2, . . . , N. Specifically, it is determined whetherat step S26 the column number n is set to “1” and whether at step S27the column number n is N columns or less of the check matrix H. If thecolumn number n is N columns or less of the check matrix H, columnprocessing regarding the nth column is executed (step S28), the columnnumber n is incremented (step S29), and the processing returns to theroutine of step S27.

More specifically, the column processing can be executed by calculatingthe prior value β_(m, n) corresponding to the non-zero element of mthrow and nth column of the check matrix H in the order of column numbern=1, 2, . . . , N according to the following Formula (5).

$\begin{matrix}{\beta_{m,n} = {\prod\limits_{m^{\prime} \in {{B{(n)}}\backslash m}}\; \alpha_{m^{\prime},n}}} & (5)\end{matrix}$

Here, B(n) is a set of the row number (row index) corresponding to thenon-zero number existing in the nth column of the check matrix H. B(n)\mrepresents a set in which the element m has been removed from the setB(n). With the Tanner graph shown in FIG. 8, for example, B(2)={1, 2,3}, and B(2)\3={1, 2}. To explain the calculation method of the priorvalue β_(2, 3) using the Tanner graph, as shown in FIG. 9C, the variablenode v₂ calculates the prior value β_(2, 3) based on a message supplied,via the edge, from the check nodes m₁, m₂ designated in the set B(2)\3.The check node m₃ updates the old prior value with the new prior valueβ_(2, 3) supplied from the variable node v₂.

After the routine of foregoing steps S26 to S29 is complete, temporarydeduced words e=(e₁, e₂, . . . , e_(N)) are calculated based on harddecision (step S30). Specifically, the temporary deduced words e_(k) canbe calculated according to the following Formula (6).

$\begin{matrix}{e_{k} = \left\{ \begin{matrix}{0,} & {{{if}\mspace{14mu} {{sign}\left( {\lambda_{k} + {\sum\limits_{m^{\prime} \in {B{(k)}}}a_{m^{\prime},k}}} \right)}} = {+ 1}} \\{1,} & {{{if}\mspace{14mu} {{sign}\left( {\lambda_{k} + {\sum\limits_{m^{\prime} \in {B{(k)}}}a_{m^{\prime},k}}} \right)}} = {- 1}}\end{matrix} \right.} & (6)\end{matrix}$

Subsequently, the check matrix H and the temporary deduced words e=(e₁,e₂, . . . , e_(N)) are used to calculate the syndrome S=H·eT accordingto the following Formula (7) (step S31).

S=H·(e ₁ , e ₂ , . . . , e _(n))^(T)=(0, 0, . . . 0)^(T).  (7)

Here, T is a transposition symbol, and e^(T) is a matrix of N row and 1column obtained by transposing the vector e=(e₁, e₂, . . . , e_(N)) asthe matrix of 1 row and N column representing the temporary deducedwords. If the second error correction decoder 26 determines that thesyndrome S includes a non-zero element (step S32), it increments thevariable i (step S33), and returns the processing to step S21. When thevariable i exceeds the maximum iteration count imax (step S21), thesecond error correction decoder 26 executes error processing such ascreating an error flag (step S34), and thereby ends the decodingprocessing. Meanwhile, if the second error correction decoder 26determines that all elements of the syndrome S are zero (step S32), itoutputs the temporary deduced word e as the deduced word, and therebyends the decoding processing.

Although the Gallager function φ (x) is used in the foregoing rowprocessing (step S24), the hardware design for calculating the value ofthe Gallager function is not easy. Thus, it would be realistic to use alook-up table (LUT) storing the function values, but an LUT requiresenormous memory capacity. In light of the above, if it is desirable toexecute simple row processing with a small memory capacity, it isdesirable to approximate the Gallager function φ (x). The approximatevalue of the outer value αm, n can be calculated according to thefollowing approximation Formulas (7a), (7b).

$\begin{matrix}{\alpha_{m,n} \cong {{\frac{1}{A}{\prod\limits_{n^{\prime} \in {{A{(m)}}\backslash \; n}}\; {{{sign}\begin{pmatrix}{\lambda_{n^{\prime}} +} \\\beta_{m,n^{\prime}}\end{pmatrix}} \cdot {\min\limits_{n^{\prime} \in {{A{(m)}}\backslash \; n}}\left( {{\lambda_{n^{\prime}} + \beta_{m,n^{\prime}}}} \right)}}}} - {c.}}} & \left( {7\; a} \right) \\{{{\alpha_{m,n} \cong {\prod\limits_{n^{\prime} \in {{A{(m)}}\backslash \; n}}\; {{{sign}(q)} \cdot {\max \left( {{{q} - B},0} \right)}}}},{where}}{q = {\prod\limits_{n^{\prime} \in {{A{(m)}}\backslash \; n}}\; {{{sign}\left( {\lambda_{n^{\prime}} + \beta_{m,n^{\prime}}} \right)} \cdot {\min\limits_{n^{\prime} \in {{A{(m)}}\backslash \; n}}{\left( {{\lambda_{n^{\prime}} + \beta_{m,n^{\prime}}}} \right).}}}}}} & \left( {7\; b} \right)\end{matrix}$

In Formula (7a), A is a non-zero normalizing constant, and c is anarbitrary constant. In Formula (7b), B is an offset constant.

As described above, with the decoding algorithm (Sum-Product decodingmethod) of the LDPC code, it is not possible to detect the accurateposition of a lost bit. However, with algebraic error correctiondecoding such as RS decoding, it is possible to detect the accurateposition of a lost bit. With the error correction decoding part 22Aaccording to the first embodiment, the second error correction decoder26 uses the erasure flag Er indicating the accurate position of the lostbit to execute the repetitive decoding without using the unreliablelikelihood information Ld. Therefore, in comparison to conventionaltechnology, it is possible to realize error correction decoding withextremely high performance of correcting random errors and burst errors.In addition, it is also possible to perform highly sophisticated errorcorrection to a data series which could not be corrected withconventional technology.

The decoding algorithm according to a modified example of the foregoingfirst embodiment is now explained. FIG. 10 is a flowchart showing theroutine of the decoding processing to be performed by the second errorcorrection decoder 26. The flowchart of FIG. 10 includes steps S20 toS33 shown in FIG. 7, and is characterized in that steps S18, S19 havebeen added before step S20.

Upon referring to FIG. 10, at step S18, the second error correctiondecoder 26 determines whether the current decoding processing is theinitial processing regarding the log likelihood ratios λ₁ to λ_(N) readthe first time from the memory circuit 24. If the second errorcorrection decoder 26 determines that the current decoding processing isthe initial processing (step S18), it creates temporary deduced wordse=(e₁, e₂, . . . , e_(N)) based on hard decision and supplies thetemporary deduced words e to the first error correction decoder 27 as is(step S19). Thus, upon performing the initial decoding processing, thestandard LDPC decoding routine (step S20 to S33) is skipped. In the harddecision at step S18, the temporary deduced words e can be calculatedaccording to foregoing Formula (6) upon setting all outer values αm, nto zero.

In the foregoing case, the first error correction decoder 27 executeserror correction decoding to a series of the temporary deduced words e₁to e_(N) supplied from the second error correction decoder 26 (step S11of FIG. 6). If a lost bit is not detected in the series of the temporarydeduced words e₁ to e_(N) (step S12), and a controller (not shown) doesnot issue a command for ending the decoding processing (step S15), thesecond error correction decoder 26 returns to step S10 and continues theLDPC decoding.

Meanwhile, if the first error correction decoder 27 detects a lost bitin the series of the temporary deduced words e₁ to eN (step S12), thefirst error correction decoder 27 creates erasure flags Er₁ to Er_(N)(step S13). Subsequently, the second error correction decoder 26re-reads the log likelihood ratios λ₁ to λ_(N) from the memory circuit24 in code word units (step S14 of FIG. 6). The re-read log likelihoodratios λ₁ to λ_(N) are supplied to the selection circuit 25. Theselection circuit 25 supplies the log likelihood ratio λ_(k) to thesecond error correction decoder 26 when the value of the erasure flagErk is “0,” and supplies a predetermined value λ0 to the second errorcorrection decoder 26 in substitute for the log likelihood ratio λ_(k)when the value of the erasure flag Erk is “1.”

The second error correction decoder 26 thereafter returns to theprocessing of step S10 and executes the LDPC decoding (FIG. 10). Here,the second error correction decoder 26 determines that the currentdecoding processing regarding the re-read log likelihood ratios λ₁ toλ_(N) is not the initial processing (step S18), and thereafter executesthe routine of steps S20 to S33.

As described above, when the second error correction decoder 26 is toperform the initial decoding processing for each code word, the standardLDPC decoding routine (step S20 to S33) is skipped. Thus, the seconderror correction decoder 26 is able to cause the first error correctiondecoder 27 to create the erasure flags Er₁ to Er_(N) in a short periodof time. Accordingly, the processing time can be shortened and thethroughput can be improved.

Second Embodiment

The second embodiment of the present invention is now explained. FIG. 11is a functional block diagram showing the schematic configuration of arecording/reproduction device 1B as the second embodiment. Therecording/reproduction device 1B is configured the same as therecording/reproduction device 1A (FIG. 1) of the first embodimentexcluding the configuration of the error correction decoding part 22B.The error correction decoding part 22B includes a memory circuit 24, aselection circuit 25, a second error correction decoder 26B, and a firsterror correction decoder 27B. The configuration of the memory circuit 24and the selection circuit 25 of the error correction decoding part 22Bis the same as the configuration of the memory circuit 24 and theselection circuit 25 of the error correction decoding part 22A of thefirst embodiment.

FIG. 12 is a diagram showing an example of the configuration of theerror correction decoding part 22B of the second embodiment. As shown inFIG. 12, N log likelihood ratios λ₁, . . . , λ_(N) are supplied for eachcode word in parallel from the SISO demodulator 21 to the memory circuit24. The selection circuit 25 is configured the same as the selectioncircuit 25 shown in FIG. 4. If the predetermined value λ0 is set to “0,”in substitute for the configuration of the selection circuit 25 shown inFIG. 12, the N logic circuits 29 ₁ to 29 _(N) shown in FIG. 5 may alsobe used.

As with the second error correction decoder 26 (FIG. 5) of the firstembodiment, the second error correction decoder 26B creates harddecision values e₁, e₂, . . . , e_(N) by estimating the code word seriesbased on the likelihood information Ld according to the decodingalgorithm of the LDPC code, and supplies the hard decision values to thefirst error correction decoder 27B.

As with the first error correction decoder 27 (FIG. 4) of the firstembodiment, the first error correction decoder 27B has a function ofexecuting algebraic error correction decoding to the series of the harddecision values e₁, e₂, . . . , e_(N), and detecting a lost bit(erasure) in symbol units configured from predetermined bits. If thefirst error correction decoder 27B detects a lost bit, it creates anerasure flag Er, and additionally creates a status flag Frs having avalue (=1) showing that the decoding processing has been executed. Thestatus flag Frs is supplied to the second error correction decoder 26B.

If a lost bit is detected, the second error correction decoder 26Bre-reads the log likelihood ratios λ₁ to λ_(N) from the memory circuit24 according to the erasure flags Er₁ to Er_(N) supplied from the firsterror correction decoder 27B. Simultaneously, the selection circuit 25supplies the log likelihood ratio λi that does not correspond to theposition of the lost bit among the log likelihood ratios λ₁ to λ_(N)read from the memory circuit 24 to the second error correction decoder26B as is in accordance with the erasure flags Er₁ to ErN, and suppliesa predetermined value λ₀ that invalidates the log likelihood ratio λ_(j)to the second error correction decoder 26 in substitute for the loglikelihood ratio λ_(j) that corresponds to the position of the lost bit.

The processing routine of the foregoing error correction decoding part22B is now explained with reference to FIG. 13 and FIG. 14. FIG. 13 is aflowchart schematically explaining a part of the processing routine tobe performed by the error correction decoding part 22B, and FIG. 14 is aflowchart showing the processing routine of the second error correctiondecoding (LDPC decoding) to be executed at step S10B of FIG. 13.

Foremost, the first error correction decoder 27B initializes the statusflag Frs and set the status flag Frs to a value other than “1” (stepS9). When the second error correction decoder 26B receives data (dataread the first time) of the log likelihood ratios λ₁ to λ_(N) from thememory circuit 24 via the selection circuit 25, it calculates thetemporary deduced words e₁ to eN by executing the LDPC decoding based onthe log likelihood ratios λ₁ to λ_(N) (step S10B). Here, the first errorcorrection decoder 27B sets the value of the erasure flags Er₁ to Er_(N)to be supplied to the selection circuit 25 to the initial value (=“0”).Thus, the selection circuit 25 supplies the data of all log likelihoodratios λ₁ to λ_(N) received from the selection circuit 25 to the seconderror correction decoder 26B as is.

In the foregoing case, upon referring to FIG. 14, the second errorcorrection decoder 26B determines whether the value of the status flagFrs is a value other than “1” (step S40). Subsequently, the same routineas the LDPC decoding (step S20 to S34) shown in FIG. 7 is executed. Atstep S32, if the second error correction decoder 26B determines that thesyndrome S includes a non-zero element, it increments the variable i(step S33), and thereafter determines whether the variable i coincideswith a predetermined limit imin (for instance, once or twice) (stepS41). If it is determined that the variable i coincides with the limitimin, the second error correction decoder 26B outputs the temporarydeduced words e=(e₁, . . . , e_(N)). Meanwhile, it is determined thatthe variable i does not coincide with the limit imin, the second errorcorrection decoder 26B returns the processing to step S21.

Thus, if all elements of the syndrome S become zero before the iterationcount i reaches the limit imin (step S32), the second error correctiondecoder 26B outputs the deduced words e=(e₁, . . . , e_(N)), and, if theiteration count reaches the limit imin before all elements of thesyndrome S become zero, the second error correction decoder 26B outputsthe temporary deduced words e=(e₁, . . . , e_(N)). The user can set thelimit imin to an arbitrary value.

Returning to the flowchart of FIG. 13, the first error correctiondecoding is subsequently executed (step S11). Specifically, the firsterror correction decoder 27B performs algebraic error correctiondecoding such as RS decoding to the series of the hard decision value asthe temporary deduced words or deduced words supplied from the seconderror correction decoder 26B, and outputs the decoding result as theuser data Dout. If the first error correction decoder 27B detects a lostbit in the hard decision value series (step S12), the first errorcorrection decoder 27B creates the erasure flags Er₁ to Er_(N)indicating the position of the lost bit and supplies the erasure flagsEr₁ to Er_(N) to the selection circuit 25 (step S13). Moreover, thefirst error correction decoder 27B sets the value of the status flag Frsto “1” (step S13B).

After the setting of the status flag Frs (step S13B), the second errorcorrection decoder 26B re-reads the log likelihood ratios λ₁ to λ_(N)corresponding to the lost bit from the memory circuit 24 in code wordunits (step S14). Data (data read the second time) of the re-read loglikelihood ratios λ₁ to λ_(N) is supplied to the selection circuit 25.The selection circuit 25 supplies the log likelihood ratio λ_(k) to thesecond error correction decoder 26B when the value of the erasure flagErk is “0” and supplies a predetermined value λ0 to the second errorcorrection decoder 26B in substitute for the log likelihood ratio λ_(k)when the value of the erasure flag Erk is “1.” Subsequently, the seconderror correction decoder 26B returns the processing to step S10B andexecutes the LDPC decoding.

In the foregoing case, upon referring to FIG. 14, the second errorcorrection decoder 26B determines that the value of the status flag Frsis “1” (step S40). Here, the initialization of step S20 is skipped andthe same routine as the LDPC decoding (step S21 to S34) shown in FIG. 7is executed. At step S32, if the second error correction decoder 26Bdetermines that the syndrome S includes a non-zero element (step S32),it increments the variable i (step S33), and, since it will thereafterdetermine that the variable i does not coincide with the limit imin(step S41), the second error correction decoder 26B returns the routineto step S21. Then, the decoding processing is repeatedly executed untilit is determined that the variable i exceeded the maximum iterationcount imax or that all elements of syndrome S will be zero (step S21,S32).

Returning to the flowchart of FIG. 13, the routine of steps S10B to S14is thereafter repeatedly executed until it is determined that a lost bitis not detected at step S12. If the first error correction decoder 27Bdoes not detect a lost bit in the series of the hard decision values e₁to e_(N) at step S12 and a controller (not shown) does not issue acommand for ending the decoding processing (step S15), the second errorcorrection decoder 26B returns to step S9 and continues the LDPCdecoding. Meanwhile, if a command for ending the decoding processing isissued (step S15), the foregoing decoding processing is ended.

As described above, the second error correction decoder 26B outputs thetemporary deduced words before the iteration count i reaches the limitimin even in cases where all elements off the syndrome S will not becomezero (step S32 of FIG. 14) with respect to the log likelihood ratios λ₁to λ_(N) read the first time from the memory circuit 24 (step S41).Thus, the second error correction decoder 26B is able to cause the firsterror correction decoder 27B to create the erasure flags Er₁ to Er_(N)in a short period of time. Accordingly, the processing can be shortenedand the throughput can be improved.

Third Embodiment

The third embodiment of the present invention is now explained. FIG. 15is a functional block diagram showing the schematic configuration of arecording/reproduction device 1C as the third embodiment. Therecording/reproduction device 1C is configured the same as therecording/reproduction device 1A (FIG. 1) of the first embodimentexcluding the SISO demodulator 21P and the error correction decodingpart 22C. Whereas the SISO demodulator 21 of the first embodimentoutputs the likelihood information Ld as parallel data, the SISOdemodulator 21P of the third embodiment outputs the likelihoodinformation Ld as serial data.

The error correction decoding part 22C includes an SP converter(serial-parallel converter) 23, a memory circuit 24, a selection circuit25, a second error correction decoder 26, a first error correctiondecoder 27C, and a lost position detection part 40. The configuration ofthe memory circuit 24, the selection circuit 25 and the second errorcorrection decoder 26 shown in FIG. 15 is the same as the configurationof the memory circuit 24, the selection circuit 25 and the second errorcorrection decoder 26 of the error correction decoding part 22A in thefirst embodiment. The first error correction decoder 27C has the samedecoding function as the first error correction decoder 27 (FIG. 1) ofthe first embodiment excluding the point that it does not have thefunction of creating erasure flags Er.

The lost position detection part 40 detects a lost bit in the series ofthe likelihood information Ld and creates an erasure flag Ea indicatingthe position of the detected lost bit. The selection circuit 25 suppliesthe log likelihood ratio that does not correspond to the position of thelost bit in the data series read from the memory circuit 24 to thesecond error correction decoder 26 as is in accordance with the erasureflag Ea, and supplies a predetermined value that invalidates the loglikelihood ratio to the second error correction decoder 26 in substitutefor the log likelihood ratio that corresponds to the position of thelost bit.

FIG. 16 is a diagram showing an example of the configuration of theerror correction decoding part 22C of the third embodiment. Serial dataof the likelihood information Ld is supplied from the SISO demodulator21P to the SP converter 23. As shown in FIG. 16, the SP converter 23converts the serial data of the likelihood information Ld into paralleldata indicating the N log likelihood ratios λ₁ to λ_(N) in code wordunits, and supplies this to the memory circuit 24. The selection circuit25 is configured the same as the selection circuit 25 shown in FIG. 4.However, the selection circuit 25 selects either the log likelihoodratio λ_(k) or the predetermined value λ0 that invalidates the loglikelihood ratio λ_(k) according to the value (“0” or “1”) of theerasure flag Eak supplied from the lost position detection part 40, andsupplies the selected value to the second error correction decoder 26.Incidentally, if the predetermined value λ₀ is set to “0,” the N logiccircuits 29 ₁ to 29 _(N) shown in FIG. 5 may be used in substitute forthe configuration of the selection circuit 25 shown in FIG. 16.

As shown in FIG. 16, the lost position detection part 40 includes anextraction control part 41, a gate circuit 42, an SP converter(serial-parallel converter) 43, and an error correction decoder (RSdecoder) 44. The extraction control part 41 and the gate circuit 42 havea code extraction function of extracting the MSB (most significant bit)of likelihood information of the user data area and the data areacorresponding to the outer code among the series of the likelihoodinformation Ld supplied from the SISO demodulator 21P. When theextraction control part 41 receives a reset pulse St from the controller(not shown), it creates an extraction control signal Eb designating theuser data area and the data area corresponding to the outer code whilesynchronizing with a clock CLK. The gate circuit 42 extracts the MSB oflikelihood information of the data area according to the extractioncontrol signal Eb. The SP converter 43 converts the serial dataconfigured from the extracted MSB of likelihood information intoparallel data in code word units, and supplies this to the errorcorrection decoder 44.

FIG. 17 to FIG. 19 are diagrams showing a part of the circuitconfiguration of the extraction control part 41. FIG. 17 shows thecircuit configuration for extracting the data block and the outer codeblock having the error correction code format of FIG. 2A, FIG. 18 showsthe circuit configuration for extracting the data block and the outercode block having the error correction code format of FIG. 2B, and FIG.19 shows the circuit configuration for extracting the data block and theouter code block from the code block having the error correction codeformat of FIG. 3.

With the circuit shown in FIG. 17, a counter 50 resets the discretevalue of the K bit to the initial value (=“0”) according to the resetpulse St and starts the pulse count operation of the clock CLK, andthereafter creates a discrete value within the range of “0” to “a1−1.”The comparator 51 supplies the 1 bit extraction control signal Eb havingthe value of “1” to the gate circuit 42 if the discrete value outputfrom the counter 50 is within the range (“0” to “a2−1”) corresponding tothe length in the columnwise direction of the data block and the outercode block of FIG. 2A. Here, the gate circuit 42 transfers thelikelihood information to the SP converter 43. Meanwhile, when thediscrete value exceeds the range (“0” to “a2−1”) corresponding to thecode length of the data block and the outer code block of FIG. 2A, [thecomparator 51] supplies a 1 bit extraction control signal Eb having avalue of “0” to the gate circuit 42. Here, the gate circuit 42 blocksthe likelihood information.

With the circuit shown in FIG. 18, the first counter 52 resets thediscrete value of the K₁ bit to the initial value (=“0”) according tothe reset pulse St and starts the pulse count operation of the clockCLK, and thereafter creates a discrete value within the range of “0” to“c1−1.” The first comparator 53 supplies a 1 bit output having a valueof “1” to the AND gate 54 when the discrete value output from the firstcounter 52 coincides with the value (=“c1−1”) corresponding to thelength in the columnwise direction of the code block of FIG. 2B. If thediscrete value does not coincide with the “c1−1,” the first comparator53 supplies a 1 bit output having a value of “0” to the AND gate 54. TheAND gate 54 supplies the clock CLK to the second counter 55 only whenthe output value of the first comparator 53 is “1.” Meanwhile, if theoutput value of the first comparator 53 is “0,” the output value of theAND gate 54 is fixed to “0.” Here, the count operation of the secondcounter 55 is stopped to inhibit power consumption. The clock that issupplied from the AND gate 54 to the second counter 55 as describedabove is referred to as a gated clock. The first counter 52, the firstcomparator 53 and the AND gate 54 are a circuit group designating thecolumnwise direction range of the data area of the data block and theouter code block of FIG. 2B.

Moreover, the second counter 55 resets the discrete value of the K₂ bitto the initial value (=“0”) according to the reset pulse St and startsthe pulse count operation of the gated clock, and thereafter creates adiscrete value within the range of “0” to “d1−1.” The second comparator56 supplies a 1 bit extraction control signal Eb having a value of “1”if the discrete value output from the second counter 55 is within therange (“0” to “d2−1”) corresponding to the length in the line writingdirection of the data block and the outer code block of FIG. 2B. If thediscrete value exceeds the range (“0” to “d2−1”) of FIG. 2B, the secondcomparator 56 supplies a 1 bit extraction control signal Eb having avalue of “0.”

Subsequently, with the circuit shown in FIG. 19, the first counter 60resets the discrete value of the K₁ bit to the initial value (=“0”)according to the reset pulse St and starts the pulse count operation ofthe clock CLK, and thereafter creates a discrete value within the rangeof “0” to “e1−1.” The first comparator 61 supplies a 1 bit output havinga value of “1” to the first AND gate 62 and the second AND gate 65 ifthe discrete value output from the first counter 60 coincides with thevalue (=“e1−1”) corresponding to the length in the columnwise directionof each code block of FIG. 3. If the discrete value does not coincidewith “e1−1,” the first comparator 61 supplies a 1 bit output having avalue of “0” to the first AND gate 62 and the second AND gate 65. Thefirst AND gate 62 outputs the gated clock through the clock CLK onlywhen the output value of the first comparator 61 is “1.” Meanwhile, ifthe output value of the first comparator 61 is “0,” the output value ofthe first AND gate 62 and the second AND gate 65 is fixed to “0,” andthe count operation of the second counter 63 and the third counter 66 isstopped. The first counter 60, the first comparator 61, the first ANDgate 62 and the second AND gate 65 are a circuit group designating thecolumnwise direction range of the data area of the data block and theouter code block in each code block of FIG. 3.

In addition, the second counter 63 resets the discrete value of the K₂bit to the initial value (=“0”) according to the reset pulse St andstarts the pulse count operation of the gated clock supplied from thefirst AND gate 62, and thereafter creates a discrete value within therange of “0” to “f1−1.” The second comparator 64 supplies a 1 bit outputhaving a value of “1” to the second AND gate 65 if the discrete valueoutput from the second counter 63 coincides with the value “f1−1”corresponding to the length in the line writing direction of each codeblock of FIG. 3. If the discrete value does not coincide with “f1−1,”the second comparator 64 supplies a 1 bit output having a value of “0”to the second AND gate 65. The second AND gate 65 supplies the gatedclock to the third counter 66 only when the output value of the firstcomparator 61 is “1” and the output value of the second comparator 64 is“1.” However, if the output value of the second comparator 64 is “0,”the count operation of the third counter 66 is stopped since the outputvalue of the AND gate 65 is fixed to “0.” The second counter 63, thesecond comparator 64 and the second AND gate 65 are a circuit groupdesignating the line writing direction range of the data area of thedata block and the outer code block of FIG. 3.

Moreover, the third counter 66 resets the discrete value of the K₃ bitto the initial value (=“0”) according to the reset pulse St and startsthe pulse count operation of the gated clock supplied from the secondAND gate 65, and thereafter creates a discrete value [within the range]of “0” to “g1−1.” The third comparator 67 supplies a 1 bit extractioncontrol signal Eb having a value of “1” if the discrete value outputfrom the third counter 66 is within the range (“0” to “g2−1”) excludingthe inner code block of FIG. 3. If the discrete value exceeds theforegoing range (“0” to “g2−1”), the third comparator 67 supplies a 1bit extraction control signal Eb having a value of “0.”

The error correction decoder 44 shown in FIG. 16 has a function ofdetecting a lost bit (erasure) in symbol units by performing algebraicerror correction decoding to an MSB series of log likelihood ratios λ₁to λ_(N) supplied in parallel from the SP converter 43. If a lost bit isdetected, the error correction decoder 44 creates an erasure flag Eaindicating the position of the lost bit, and supplies this to theselection circuit 25 and the second error correction decoder 26.

The processing routine to be performed by the foregoing error correctiondecoding part 22C is explained with reference to FIG. 20. FIG. 20 is aflowchart schematically explaining a part of the processing routine tobe performed by the error correction decoding part 22C.

As described above, the lost position detection part 40 executes thelost position detection processing by performing algebraic errorcorrection decoding to an MSB series of log likelihood ratios λ₁ toλ_(N) of a user data area and a data area (area including the data blockand the outer code block) corresponding to the outer code (step S40).Here, if a lost bit is detected (step S41), the lost position detectionpart 40 creates erasure flags Ea₁ to Ea_(N) and supplies the erasureflags Ea₁ to Ea_(N) to the selection circuit 25 and the second errorcorrection decoder 26 (step S42). The selection circuit 25 supplies thelog likelihood ratio λ_(k) read from the memory circuit 24 to the seconderror correction decoder 26 if the value of the erasure flag Eak is “0,”and supplies a predetermined value λ0 to the second error correctiondecoder 26 in substitute for the log likelihood ratio λ_(k) if the valueof the erasure flag Eak is “1.” Meanwhile, if a lost bit is not detected(step S41), the routine of step S42 is skipped.

Subsequently, the second error correction decoder 26 executes the sameprocessing as the LDPC decoding (steps S20 to S33) shown in FIG. 7 andsupplies a series of deduced words e₁ to eN to the first errorcorrection decoder 27C (step S43). The first error correction decoder27C performs algebraic error correction decoding to the series of thededuced words e₁ to e_(N) and outputs the decoding result as output dataDout (step S44). In addition, if a controller (not shown) does not issuea command for ending the decoding processing (step S45), the processingis returned to step S40. Meanwhile, if a command for ending the decodingprocessing is issued (step S45), the foregoing decoding processing isended.

As described above, in the third embodiment, the lost position detectionpart 40 detects the position of a lost bit by executing algebraicdecoding of the outer code before the second error correction decoder 26executes the LDPC decoding of the inner code. The second errorcorrection decoder 26 is able to execute repetitive decoding using theerasure flags Ea₁ to Ea_(N) indicating the accurate position of the lostbit without having to use unreliable likelihood information Ld.Accordingly, it is possible to realize error correction decoding withhigh throughput and high precision.

Incidentally, in the foregoing third embodiment, the error correctiondecoding part 22C includes an SP converter 23, and the lost positiondetection part 40 includes an SP converter 43 as shown in FIG. 16.However, the SP converters 23, 43 are not necessarily essentialconstituent elements. If the error correction decoding part 22C does notinclude an SP converter 23, the memory circuit 24 simply needs to have aconfiguration capable of storing serial data and outputting paralleldata. Moreover, if the lost position detection part 40 does not includean SP converter 43, the error correction decoder 44 simply needs to havea configuration capable of processing the serial output of the gatecircuit 42.

Fourth Embodiment

The fourth embodiment of the present invention is now explained. FIG. 21is a functional block diagram showing the schematic configuration of arecording/reproduction device 1D as the fourth embodiment. Therecording/reproduction device 1D has both the function of therecording/reproduction device 1A (FIG. 1) of the first embodiment andthe function of the recording/reproduction device 1C (FIG. 15) of thethird embodiment. The recording/reproduction device 1D is configured thesame as the recording/reproduction device 1A (FIG. 1) of the firstembodiment excluding the SISO demodulator 21P and the error correctiondecoding part 22D. While the SISO demodulator 21 of the first embodimentoutputs the likelihood information Ld as parallel data, the SISOdemodulator 21P of the fourth embodiment outputs the likelihoodinformation Ld as serial data.

The error correction decoding part 22D includes an SP converter 23, amemory circuit 24, a selection circuit 25D, a second error correctiondecoder 26D, a first error correction decoder 27, and a lost positiondetection part 40. The configuration of the memory circuit 24 and thefirst error correction decoder 27 of FIG. 21 is the same as theconfiguration of the memory circuit 24 and the first error correctiondecoder 27 of the error correction decoding part 22A of the firstembodiment. Moreover, the configuration of the lost position detectionpart 40 and the SP converter 23 of FIG. 21 is the same as theconfiguration of the lost position detection part 40 and the SPconverter 23 (FIG. 15) of the third embodiment.

The second error correction decoder 26D has the same decoding functionas the second error correction decoder 26 of the error correctiondecoding part 22A in the first embodiment, and is also able to re-read adata series of log likelihood ratios from the memory circuit 24according to the erasure flag Ea from the lost position detection part40 or the erasure flag Er from the first error correction decoder 27.The selection circuit 25D supplies the log likelihood ratio that doesnot correspond to the position of the lost bit in the data series readfrom the memory circuit 24 to the second error correction decoder 26D asis in accordance with the erasure flag Er or Ea, and supplies apredetermined value that invalidates the log likelihood ratio to thesecond error correction decoder 26D in substitute for the log likelihoodratio that corresponds to the position of the lost bit.

FIG. 22 is a diagram showing an example of the configuration of theerror correction decoding part 22D. Serial data of the likelihoodinformation Ld is supplied from the SISO demodulator 21P to the SPconverter 23. As shown in FIG. 22, the SP converter 23 converts theserial data of the likelihood information Ld into parallel dataindicating the N log likelihood ratios λ₁ to λ_(N) in code word units,and supplies this to the memory circuit 24. The selection circuit 25D isconfigured the same as the selector groups 28 ₁ to 28N shown in FIG. 4,and additionally includes an OR gate 31 _(k) for performing OR operationto the bits of the erasure flags Eak, Erk (k is an arbitrary integerfrom 1 to N). Output of the OR gates 31 ₁ to 31 _(N) is supplied to thecontrolled terminal of the selectors 28 ₁ to 28N, respectively.

The processing routine to be performed by the foregoing error correctiondecoding part 22D is now explained with reference to FIG. 23. FIG. 23 isa flowchart schematically showing a part of the processing routine to beperformed by the error correction decoding part 22D.

As described above, the lost position detection part 40 executes thelost position detection processing by performing algebraic errorcorrection decoding to an MSB series of log likelihood ratios λ₁ toλ_(N) of a user data area and a data area (area including the data blockand the outer code block) corresponding to the outer code (step S40).Here, if a lost bit is detected (step S41), the lost position detectionpart 40 creates erasure flags Ea₁ to Ea_(N) and supplies the erasureflags Ea₁ to Ea_(N) to the selection circuit 25D and the second errorcorrection decoder 26D (step S42). The selection circuit 25 supplies thelog likelihood ratio λ_(k) read from the memory circuit 24 to the seconderror correction decoder 26 if the value of the erasure flag Eak is “0,”and supplies a predetermined value λ0 to the second error correctiondecoder 26 in substitute for the log likelihood ratio λ_(k) if the valueof the erasure flag Eak is “1.” Meanwhile, if a lost bit is not detected(step S41), the routine of step S42 is skipped.

Subsequently, the second error correction decoder 26D executes the sameprocessing as the LDPC decoding (steps S20 to S33) shown in FIG. 7 andsupplies a series of deduced words e₁ to eN to the first errorcorrection decoder 27 (step S43). The first error correction decoder 27performs algebraic error correction decoding to the series of thededuced words e₁ to e_(N) and outputs the decoding result as output dataDout (step S44). Here, if a lost bit is detected (step S46), the firsterror correction decoder 27 creates erasure flags Er₁ to Er_(N) andsupplies the erasure flags Er₁ to Er_(N) to the selection circuit 25Dand the second error correction decoder 26D (step S47).

After the creation of the erasure flags Er₁ to Er_(N) (step S47), thesecond error correction decoder 26D re-reads the log likelihood ratiosλ₁ to λ_(N) corresponding to the lost bit from the memory circuit 24 incode word units (step S48). Data of the re-read log likelihood ratios λ₁to λ_(N) is supplied to the selection circuit 25D. Here, the selectioncircuit 25D supplies the log likelihood ratio λ_(k) to the second errorcorrection decoder 26D if the value of the erasure flag Erk is “0,” andsupplies a predetermined value λ0 to the second error correction decoder26D in substitute for the log likelihood ratio λ_(k) if the value of theerasure flag Erk is “1.” Then, the second error correction decoder 26returns to the processing of step S43 and executes LDPC decoding. Theroutine of steps S43 to S48 is thereafter repeatedly executed until itis determined that a lost bit is not detected at step S46.

If the first error correction decoder 27 does not detect a lost bit inthe series of the deduced words e₁ to eN at step S46, and a controller(not shown) does not issue a command to end the decoding processing(step S45), the processing returns to step S40 and the decodingprocessing continues. Meanwhile, if a command for ending the decodingprocessing is issued (step S45), the foregoing decoding processing isended.

Incidentally, in the foregoing fourth embodiment, the error correctiondecoding part 22D includes an SP converter 23, and the lost positiondetection part 40 includes an SP converter 43 as shown in FIG. 22.However, the SP converters 23, 43 are not necessarily essentialconstituent elements. If the error correction decoding part 22D does notinclude an SP converter 23, the memory circuit 24 simply needs to have aconfiguration capable of storing serial data and outputting paralleldata. Moreover, if the lost position detection part 40 does not includean SP converter 43, the error correction decoder 44 simply needs to havea configuration capable of processing the serial output of the gatecircuit 42.

Fifth Embodiment

The fifth embodiment of the present invention is now explained. FIG. 24is a functional block diagram showing the schematic configuration of arecording/reproduction device 1E as the fifth embodiment. Therecording/reproduction device 1E has the same functions as therecording/reproduction device 1D (FIG. 21) of the fourth embodimentexcluding the error correction decoding part 22E. The error correctiondecoding part 22E has the same configuration as the SP converter 23, thememory circuit 24, the selection circuit 25D, the second errorcorrection decoder 26D and the first error correction decoder 27 of theerror correction decoding part 22D (FIG. 21 and FIG. 22) in the fourthembodiment, and additionally includes a selection circuit 70 and a lostposition detection part 40E.

FIG. 25 is a diagram showing an example of the configuration of theerror correction decoding part 22E of the fifth embodiment. As shown inFIG. 25, the lost position detection part 40E includes the sameextraction control part 41, gate circuit 42 and SP converter 43 as thelost position detection part 40 of the foregoing fourth embodiment. Thelost position detection part 40E includes an error correction decoder44E comprising a decoding status determination part 44 s, and the errorcorrection decoder 44E has, in addition to the function of detecting alost bit by executing algebraic decoding, a function of outputting thedecoding result DR₂ of such algebraic decoding.

As described above, the error correction decoder 44E has a function ofdetecting a lost bit (erasure) in symbol parts by performing algebraicerror correction decoding to an MSB series of log likelihood ratios λ₁to λ_(N) extracted from the gate circuit 42. The decoding statusdetermination part 44 s is able to determine four types of decodingstates; namely, 1) state with no symbol error, 2) state in which thenumber of symbol errors is within a correctable symbol count, 3) statein which the number of symbol errors is within a symbol count where theerror position can be detected, and 4) state in which the number ofsymbol errors exceeds a symbol count where the error position can bedetected. The decoding status determination part 44 s determines thatthe possibility of foregoing state 1) or state 2) is high if the SNR(signal-to-noise ratio) is high. In addition, in the case of foregoingstate 4), it would be appropriate to perform processing as beingnon-reproducible.

Based on the foregoing perspective, if the decoding status determinationpart 44 s determines that the decoding state is foregoing state 1) andstate 2), it creates a switch control signal Sf for causing theselection circuit 70 to select the decoding output DR₂ of the errorcorrection decoder 44E. In addition, if the decoding statusdetermination part 44 s determines that the decoding state is foregoingstate 4), it creates a switch control signal Sf for causing theselection circuit 70 to select the decoding output DR₁ of the firsterror correction decoder 27.

Moreover, if the decoding status determination part 44 s determines thatthe decoding state is foregoing state 3), it determines that the[decoding state] is of an error correction disabled state in which alost bit was detected, and creates erasure flags Ea₁ to Ea_(N).Simultaneously, the decoding status determination part 44 s creates aswitch control signal Sf for causing the selection circuit 70 to selectthe decoding output DR₁ of the first error correction decoder 27.

As described above, in the fifth embodiment, since the optimal decodingprocessing can be executed according to the decoding state detected withthe lost position detection part 40, it is possible to improve the errorcorrection performance and throughput.

Incidentally, in the foregoing fifth embodiment, the error correctiondecoding part 22E includes an SP converter 23, and the lost positiondetection part 40E includes an SP converter 43 as shown in FIG. 25.However, the SP converters 23, 43 are not necessarily essentialconstituent elements. If the error correction decoding part 22E does notinclude an SP converter 23, the memory circuit 24 simply needs to have aconfiguration capable of storing serial data and outputting paralleldata. Moreover, if the lost position detection part 40[E] does notinclude an SP converter 43, the error correction decoder 44 simply needsto have a configuration capable of processing the serial output of thegate circuit 42.

1. A decoding device for performing error correction decoding of encodeddata formed from a combination of an outer code for first errorcorrection and an inner code for second error correction, the devicecomprising: a demodulator for demodulating the encoded data and creatinga data series of likelihood information values; a memory circuit fortemporarily storing the data series of likelihood information values; asecond error correction decoder for creating a hard decision valueseries by executing repetitive decoding for the second error correctionbased on the data series of likelihood information values read from thememory circuit; and a first error correction decoder for detecting alost bit in the hard decision value series by executing algebraicdecoding for the first error correction to the hard decision valueseries and creating an erasure flag indicating a position of thedetected lost bit, wherein the second error correction decoder creates aseries of temporary deduced words or deduced words by executing harddecision based on the data series of likelihood information values readfor the first time from the memory circuit, and wherein the first errorcorrection decoder detects a lost bit in the series of temporary deducedwords or deduced words by executing the algebraic decoding to thecreated series of temporary deduced words or deduced words and createsan erasure flag indicating a position of the detected lost bit.
 2. Thedecoding device according to claim 1, wherein the second errorcorrection decoder includes a selector for selecting a value of either alikelihood information value of the data series re-read from the memorycircuit or the predetermined value according to the erasure flag, andwherein the selector selects the likelihood information value when there-read likelihood information value of the data series does notcorrespond to the position of the lost bit, and selects thepredetermined value when the re-read likelihood information value of thedata series corresponds to the position of the lost bit.
 3. The decodingdevice according to claim 1, wherein the demodulator creates a loglikelihood ratio concerning the encoded data as the likelihoodinformation value.
 4. The decoding device according to claim 3, whereinthe inner code for second error correction is a low density parity checkcode.
 5. The decoding device according to claim 4, wherein the seconderror correction decoder executes the repetitive decoding according to aSum-Product decoding method.
 6. The decoding device according to claim1, wherein the first error correction decoder detects a lost bit in thehard decision value series in symbol parts of predetermined bits.
 7. Thedecoding device according to claim 6, wherein the outer code for firsterror correction is a Reed-Solomon code, and the first error correctiondecoder executes Reed-Solomon decoding as the algebraic decoding. 8.(canceled)
 9. (canceled)
 10. (canceled)
 11. (canceled)
 12. A decodingdevice for performing error correction decoding of encoded data formedfrom a combination of an outer code for first error correction and aninner code for second error correction, the device comprising: ademodulator for demodulating the encoded data and creating a data seriesof likelihood information values; a lost position detection part fordetecting a lost bit in the data series of likelihood information valuesand creating a first erasure flag indicating a position of the detectedlost bit; a memory circuit for temporarily storing the data series oflikelihood information values; a second error correction decoder forcreating a hard decision value series by executing repetitive decodingfor the second error correction based on the data series likelihoodinformation values read from the memory circuit when the lost bit is notdetected; and a first error correction decoder for executing algebraicdecoding for the first error correction to the hard decision valueseries, wherein when the lost bit is detected, the second errorcorrection decoder executes the repetitive decoding based on alikelihood information value not corresponding to the position of thelost bit among the data series of likelihood information values readfrom the memory circuit and a predetermined value that invalidates alikelihood information value corresponding to the position of the lostbit among the read data series of likelihood information values, andwherein the lost position detection part includes: a code extractionpart for extracting a likelihood information value of a user data areaand a data area corresponding to the outer code from the data series oflikelihood information values created by the demodulator; and an errorcorrection decoder for creating the first erasure flag by executingalgebraic decoding for the first error correction to a data series of amost significant bit of the likelihood information values extracted bythe code extraction part.
 13. The decoding device according to claim 12,wherein the first error correction decoder detects a lost bit in thehard decision value series by executing algebraic decoding for the firsterror correction to the hard decision value series, and creates a seconderasure flag indicating the position of the detected lost bit, andwherein the second error correction decoder, according to the seconderasure flag, re-reads the data series of likelihood information valuesfrom the memory circuit, and executes the repetitive decoding based on alikelihood information value not corresponding to the position of thelost bit among the re-read data series and a predetermined value thatinvalidates a likelihood information value corresponding to the positionof the lost bit among the re-read data series.
 14. (canceled)
 15. Thedecoding device according to claim 12, further comprising a selectioncircuit for selecting either decoded data supplied from the first errorcorrection decoder or decoded data supplied from the error correctiondecoder of the lost position detection part, and outputting the selecteddecoded data, wherein the error correction decoder of the lost positiondetection part includes a decoding status determination part fordetermining whether error correction can be performed when an error isdetected in the data series of the most significant bit of thelikelihood information values, and wherein the selection circuit selectsthe decoded data supplied from the first error correction decoder whenthe status determination part determines that error correction cannot beperformed, and selects the decoded data supplied from the errorcorrection decoder of the lost position detection part when the statusdetermination part determines that error correction can be performed.16. (canceled)
 17. (canceled)
 18. The decoding device according to claim13, further comprising a selection circuit for selecting either decodeddata supplied from the first error correction decoder or decoded datasupplied from the error correction decoder of the lost positiondetection part, and outputting the selected decoded data, wherein theerror correction decoder of the lost position detection part includes adecoding status determination part for determining whether errorcorrection can be performed when an error is detected in the data seriesof the most significant bit of the likelihood information values, andwherein the selection circuit selects the decoded data supplied from thefirst error correction decoder when the status determination partdetermines that error correction cannot be performed, and selects thedecoded data supplied from the error correction decoder of the lostposition detection part when the status determination part determinesthat error correction can be performed.